timing generator

A new type of timing pulse generator is designed and simulated using WINS software.

设计了一种新的产生RSFQ时钟信号的电路，并利用WINS软件对电路进行了模拟。

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The improved timing and intermittent NaCLO_2 generator, the bridge rectification cabinet of the NaCLO_2 generator and the feeding of NaCLO_2 by capsule pressure-difference pot were illustrated in the paper.

本文对研究改进后的定时间歇运行次氯酸钠发生器、次氯酸钠发生器分开式电器柜桥式整流及胶囊式压差罐投加次氯酸钠消毒液进行了阐述。

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Design of the Display Timing Generator in the LCD Scaler

LCD定标器中显示时序控制模块的设计

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Apart from the above two modules Scaler chip also includes some auxiliary parts such as the Display Timing Generator module and the microprocessor I/ O module.

这种结构可以简化寻址数据部分的复杂度，节省电路面积。除上述两个模块，定标器芯片中还包括输入模块、显示时序控制模块、微处理器接口模块等辅助模块。

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Timing generator principle, understanding the clock and timing signal waveform.

时序产生器的原理, 了解时钟和时序信号的波形.

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Singlechip frequency conversion timing PWM wave generator

单片机变频调速PWM波发生器

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Timing generator of aerospace liner CCD camera and its implementation based on ISP technology

线阵CCD相机时序发生器及其基于ISP技术的实现

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A timing adjusted ramp generator

一个定时校准的斜坡发生器

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Briefly presented the Timing Generator's functions: it generates various kinds of impulse sequence for the focal plane unit and vision processor and acts as the synchronous coordinator for time in the CCD imaging unit.

简述了线阵CCD相机中CCD成象单元的时序发生器的功能：产生焦平面组件和视频处理器所需的各种脉冲序列，在CCD成象单元工作中起着时间上同步协调的作用。

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Design of CCD Timing Signal Generator

CCD时序信号发生器的设计

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Design Practice of Timing Signal Generator Based on PC Parallel Port

基于PC并口的定时信号发生器的设计实践

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An integrative design of multi-channel CCD timing generator and data cache

CCD时序电路与数据缓存器的一体化设计

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The CCD Timing Generator's architecture and its working process were analyzed.

讨论了CCD时序发生器的组成原理及其工作过程。

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LCD controller mainly consists of three modules of host interface, display ram master and LCD timing generator.

控制器主要由三个模块组成：处理器接口模块、显存控制模块和LCD时序控制模块。

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Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and ( 216-1).

每一个集成异步通信器件包括一个可编程的波特率发生器，它能够对输入时钟进行1～216-1的分频。

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The interface relation between the CCD Timing Generator and CCD controller was also discussed.

给出了它与CCD控制器的接口关系：由CCD控制器给出的指令和数据予以控制。

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Timing generator of a high speed CCD camera using FPGA

采用FPGA的高速CCD相机的时钟发生器

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The design of Timing Generator of Scientific Grade CCD Camera Based on FPGA SCIENCE

基于FPGA的科学级CCD相机时序发生器的设计

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The main structure of the hardware including top timing control unit, bram and its timing generator, serial to parallel converter, shift register, multiplexer, processing element and multi-level adders.

硬件结构主要包括总体时序控制单元、存储单元及其时序发生器、串并转换单元、移位器、选通器、运算单元和级联加法器。

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Based on the ISP technology and by utilizing the Expert soft system, the design process of the Timing Generator and the function simulation were presented. By using the ispLSI devices, the scheme was implemented in the end.

基于在系统可编程（ISP）技术，利用相应的软件Expert System对时序发生器进行设计、编译，并且进行了功能仿真，最后采用ispLSI器件实现了该方案。

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The rows and columns are usually driven separately, with timing controlled by the timing generator.

行与列往往是分开驱动的, 其时序由时序信号发生器来控制.

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